Various methods and systems have been used to resolve or solve for device or component values in a network or circuit (generally “network”) of bi-directional devices in order to determine which values satisfy or solve the network. Typically, resolution devices are coupled to nodes via bi-directional data connections. One known system includes resolution devices that are executed in an iterative algorithm. In other words, the iterative algorithm repeatedly applies a bi-directional resolution function to the values of corresponding network nodes until the node values do not change and settle into a stable set of values, which is a solution to the network.
One conventional system is a TRAN network in a Verilog simulation. The TRAN network is a model of a circuit containing bi-directional “TRAN” elements that is expressed as a set of Verilog “TRAN” elements and “WIRE” connections. The TRAN network takes input values and processes them to produce outputs, which may be the same as or different from the node values depending on the stability of the network based on the inputs. Outputs that represent new node values replace the old node values, and the TRAN resolution functions can be applied using these “new” node values.
More particularly, a TRAN network includes internal nodes with values, resolution or TRAN devices, and bi-directional connections between one or more nodes and the TRAN resolution devices. The input values to TRAN devices can be any Verilog signal. Verilog is a well known language that is used to describe hardware components and their relationships. The resolution devices take the Verilog signals and process them using a set of resolution functions in order to resolve the network and determine stable node values.
More specifically, during initialization, all of the internal TRAN nodes are initialized to an undriven state. The value of a driver is copied into the internal node of the TRAN network that is connected to the driver. Thus, there may be some nodes that are maintained in the undriven state since they do not receive an input from a driver, and other nodes that are updated from the initial undriven state with a driver input value. The internal nodes are connected to one or more resolution devices, which execute a TRAN resolution function using the node values. More particularly, the resolution function of each resolution device is repeatedly applied to its inputs in a loop, as provided in the following pseudo-code of a conventional iterative TRAN resolution algorithm:
Tran_network_resolution (TRANs, INPUTs){  foreach INPUT {   if (driven (INPUT)) {    INPUT = driving value;   }   else {    INPUT = undriven value (1 ’bz);   }  }  change = TRUE;  while (change) {   change = FALSE;   foreach TRAN {    new_value = tran_resolution (TRAN);    change = change | new_value   }  }  for each INPUT {   schedule new value;  }}Thus, all of the TRAN resolution devices are evaluated once during each iteration. The iterations continue to generate outputs or “new” node values, which are processed until the node values become stable. Stable node values are then copied out of the internal nodes by a reader or other external device.
The conventional implementation of TRAN networks, however, can be improved. For example, regardless of whether some nodes have updated or undriven driver values, all of the resolution devices are evaluated as a result of the iterative loops of such networks. Thus, while the iterative TRAN resolution approach may be space efficient and provide a relatively compact solution, all of the resolution functions are repeatedly executed and repeatedly executed on node values that may not relevant to the analysis. Thus, an iterative TRAN analysis can take a long time to complete and is inherently inefficient. Thus, the costs and time required to model circuits and networks is unnecessarily increased. These shortcomings are amplified with more complicated systems and as more TRAN resolution devices are utilized.
An alternative prior art approach that has been used is to convert the TRAN network into an equivalent set of basic unidirectional devices, which are then evaluated using a traditional event simulator. This alternative approach may provide a more computationally efficient method compared to an iterative algorithm approach, however, it generates a substantially larger representation of the network and devices, resulting in a large event simulation that is not space efficient.
Accordingly, there exists a need for a system and method that can process and resolve networks in a more time and space efficient manner.